Design-Reuse

From Behavioral to RTL Design Flow in SystemC

This paper reports the scientific collaboration between LLR and PROSILOG. The aim of this collaboration was to show the possibility to quickly implement a system into a FPGA, using SystemC 4 as the ...
Semiconductor Engineering

Full AMS Design Flow For The IoT

The pressure for a new generation of (analog/mixed-signal) AMS design capabilities has been accelerated by the sudden demand for Internet of Things (IoT). These inexpensive devices are used in an ...
Design-Reuse

Arithmatica Updates CellMath Tools for Power Optimization and Tighter Flow Integration for Verilog Users

PALO ALTO, Calif. - April 5, 2006 - Arithmatica, Inc., the first company focused solely on using advances in silicon math algorithms to lower costs and power and increase speed for math-intensive ICs, ...
EDN

For SoC design with C++, success lies in the details

>As a consultant on the use of Verilog and VHDL for electronic design, I've observed firsthand the ever-increasing challenges designers face to implement system-on-chip (SoC) designs with current ...
Semiconductor Engineering

Combining CMOS IC And MEMS Design For IoT Edge Devices

Creating a sensor-based IoT edge device is challenging, due to the multiple design domains involved. But, creating an edge device that combines the electronics using the traditional CMOS IC flow and a ...