These programmable-logic devices combine CPLD flash configurability with an FPGA lookup-table architecture for lower-cost, logic-intensive designs. Applications traditionally supported by high-density ...

Version 5.1 of the ispLEVER programmable logic design suite adds features that include a FPGA preference flow, enhanced timing-closure and design-fit capabilities, and an IP-delivery infrastructure ...

My long running series titled "How the FPGA Came To Be" (referenced below) chronicles the development of programmable logic starting with programmable diode matrices developed and marketed by Harris ...