EDN

Low power implementation techniques for ASIC physical design

In the semiconductor domain, the operating frequency of devices and the number of transistors in a single module increase over time. In this article, we will look at widely known low power ...
EDN

Top 10 methods for ASIC power minimization — Part 2

This is the second part of a two part article focusing on power minimization in deep submicron ASICs. Part 1 illustrates five architectural methods of low power design. The focus of this part is on ...
Electronic Design

Ultra-Low-Power, Ultra-Low-Noise ASIC Breakthroughs Enable New MEMS Sensors

Often, a technological breakthrough can lead to new products and even new applications that had previously been considered fantasy. Developments in low-power, low-noise readout ASICs could open new ...
Electronic Design

5G Cellular Infrastructure and the Migration from FPGAs to Custom ASICs

As Zhengmao Li, executive vice president of the world’s biggest operator put it at MWC this year, 5G will require three times as many base stations to deliver the same coverage as LTE, will require ...
Design-Reuse

Key ASIC Berhad Signs RM1.11 Million Contract to Jointly Develop AI-Driven, Ultra-Low Power RF Navigation Chip with Middle East Partner

Key ASIC Berhad (“Key ASIC” or “the Company”), a leader in ASIC design and innovation, has signed a contract worth RM1.11 million with a navigation systems company in the Middle East to jointly ...